Yi-Wen Wang

Yi-Wen Wang

Associate Professor

Mail

Education：

  • 美國密西根州立大學 電機工程學系 博士
  • 美國密西根州立大學 電機工程學系 碩士
  • 國立交通大學 控制工程 學士

Research Interest：

  • Embedded System Design
  • VLSI Design
  • Neural Network
  1. De-Sheng Chen*, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Constrained Floorplanning for Modern SoC Design," Journal of Cybernetics and Systems, Vol. 1, No. 1, PP. 27~39, 2008-08.
  2. De-Sheng Chen*, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Constrained Floorplanning for Modern SoC Design," Journal of Cybernetics and Systems, 1, PP. 27~39, 2008-06. (SCIE,EI)
  3. De-Sheng Chen, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Fixed-Outline Floorplanning Using Robust Evolutionary Search," Engineering Applications of Artificial Intelligence, 20, PP. 821~830, 2007-06. (SCIE,EI)
  4. Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "VLSI Floorplanning with Boundary Constraints Using Generalized Polish Expression," Journal of the Chinese Institute of Engineers (JCIE), Vol.29, No.3, PP. 383~389, 2006-05. (SCIE,EI)
  5. De-Sheng Chen, Chang-Tzu Lin and Yi-Wen Wang, "A Robust Genetic Algorithm for Rectangle Packing Problem," Journal of Combinatorial Optimization (JOCO), Vol. 12, 2006-05. (SCIE,EI)
  6. Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "Modern Floorplanning with Boundary and Fixed-Outline Constraints via Genetic Clustering Algorithm," Journal of Circuits, Systems, and Computers, JCSC, Vol. 15, No. 1, PP. 107~127, 2006-02. (SCIE,EI)
  7. D.C. Su，S.F. Hwang，C.R. Dow，Y. W. Wang, "An Efficient K-hop Clustering Routing Scheme for Ad-hoc Wireless Networks," Internet Technology, Vol. 3, No. 2, PP. 139~146, 2002-04. (SCIE,EI)
  1. Huan-Teng Li, De-Sheng Chen, Yi-Wen Wang,"A Predict Policy Method for Word-Based Montgomery Modular Multiplication ," 2012 VLSI/CAD Symposium, 2012-08. Kenting, Taiwan .
  2. Huan-Teng Li, De-Sheng Chen, Yi-Wen Wang,"A Predict Policy Method for Word-Based Montgomery Modular Multiplication ," 2012 VLSI/CAD Symposium, 2012-08. Kenting, Taiwan .
  3. Che-Ming Chang, De-Sheng Chen, Y-Wen Wang,"A High-throughput Deblocking Filter With New Filtering Schedule ," 2012 International Conference on Electronics, Communication and Computer Science, 2012-06. Naning, China .
  4. C. Hung, H. Lin, D. Chen, Y. Wang,"ASIP Instruction Selection with the Encoding-Space Constraint for High Performance ," International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART 2012), 2012-05. Okinawa, Japan .
  5. Ginhsuan Li, Chiuyun Hung, De-Sheng Chen, and Yiwen Wang*,"Application-Specific Instruction sets Processor with Implicit Registers to Improve Register Bandwidth ," World Academy of Science, Engineering and Technology, 2011-06. Paris, France .
  6. De-Sheng Chen*, Po-Yu Chen, Yi-Wen Wang,"Hardware/Software Co-Design of NLMS Adaptive Filters on FPGA ," International Symposium on Consumer Electronics, 2011-06. Singapore .
  7. Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang and Yi-wen Wang*,"Application Specific Instruction set Exploration on VLIW Architectures ," International Conference on Embedded Systems and Applications, 2010-07. Las Vegas Nevada, USA .
  8. Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang and Yi-wen Wang*,"Application Specific Instruction set Exploration on VLIW Architectures ," WORLDCOMP'10, ESA'10, 2010-07. Las Vegas Nevada, USA .
  9. De-Sheng Chen*, Kui-Shun Chou, Yi-Wen Wang,"A New Block-Based Stochastic Adaptive Algorithm for Sparse Echo Cancellation ," The International Conference on Signal Processing Systems (ICSPS 2010), V1-756-V1-760, 2010-07. Dalian, China .
  10. De-Sheng Chen*, Kui-Shun Chou, Yi-Wen Wang,"A New Block-Based Stochastic Adaptive Algorithm for Sparse Echo Cancellation ," The International Conference on Signal Processing Systems, 2010-07. Dalian, China .
  11. Kui-Shun Chou, Po-Yu Chen, De-Sheng Chen*, Yiwen Wang,"Improved Partial Update NLMS Algorithm For Sparse Impulse Response Identification In VOIP ," National Symposium on Telecommunications, 2009-12. Kaohsiung, Taiwan .
  12. Bohong Chen, Yiwen Wang*, Desheng Chen, Chiuyun Hung,"Task Partition and Scheduling on Multiple Heterogeneous Application-Specific Instruction-Set Processors ," 20th VLSI Design/CAD Symposium, 2009-08. Hualien, Taiwan .
  13. Ya-Feng Shen, Chang-Tzu Lin, Ji-Ying Wu, De-Sheng Chen*, Yi-Wen Wang,"Voltage Island Problem with Interconnection Delay Consideration ," 19th VLSI Design/CAD Symposium, 2008-08. Hualien, Taiwan .
  14. Chijie Lin, Jiying Wu, Jerung Shiu, De-Sheng Chen, and Yiwen Wang*,"Performance Improvement using Application-Specific Instructions under Hardware Constraints ," International Conference on embedded Software and Systems, 2008-07. Chengdu, China .
  15. Jiying Wu, Chijie Lin, De-Sheng Chen, Yiwen Wang*,"Memory Models for an Application-Specific Instruction-set Processor Design Flow ," International Conference on Embedded Software and Systems, 2008-07. Chengdu, China .
  16. None,"2008國際嵌入式系統及嵌入式軟件會議 ," 2008國際嵌入式系統及嵌入式軟件會議, 2008-07. 中國大陸 .
  17. Chijie Lin, Jiying Wu, Jerung Shiu, Desheng Chen, Yiwen Wang,"Performance Improvement using Application-Specific Instructions under Hardware Constrains ," 18th VLSI Design/CAD Symposium, 2007-08. Hualien, Taiwan .
  18. Jiying Wu, Chijie Lin, Jerung Shiu, Desheng Chen, Yiwen Wang,"A Design Methodology for Application-Specific Instruction-set Processors with Memory Access Considerations ," 18th VLSI Design/CAD Symposium, 2007-08. Hualien, Taiwan .
  19. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, Ching-Hwa,"Noise-Aware Floorplanning for Fast Power Supply Network Design ," The IEEE International Symposium on Circuits and Systems (ISCAS), 2007-05. New Orleans, USA .
  20. Shengjyi Yang, Chijie Lin, Chiu Yun Hung, Jiying Wu, Yiwen Wang,"Application-Specific Instruction Generation for SOC Processors ," The IEEE International Symposium on Circuits and Systems (ISCAS), 2007-05. New Orleans, USA .
  21. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen*, Yi-Wen Wang, and Ching-Hwa Cheng,"Noise-Aware Floorplanning for Fast Power Supply Network Design ," International Symposium on Circuits and Systems, 2007-05. New Orlean, U.S.A .
  22. Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Jiawei Chang, De-Sheng Chen, and Yi-Wen Wang,"Automatic Application-Specific Instruction Generation for SOC Processors ," 17th VLSI Design/CAD Symposium, 2006-08. Hualien, Taiwan .
  23. Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, and Ching-Hwa Cheng,"A Novel Design Methodology for SI Aware Floorplanning Designs ," 17th VLSI Design/CAD Symposium, 2006-08. Hualien, Taiwan .
  24. Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Multilevel Genetic Placement Algorithm for Large-Scale Mixed-Size SOC Designs ," The 16th VLSI Design/CAD Symposium, ., 2005-08. Hualien, Taiwan .
  25. Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang,"Modern Floorplanning with Abutment and Fixed-Outline Constraints ," ISCAS 2005, pp.6214-6217, 2005-05. Kobe, Japan .
  26. Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang, Po-Shu Shih, and Ying-Ren Xhao,"Fixed-Outline Floorplanning with Abutment Constraints ," The 15th VLSI Design/CAD Symposium, ., 2004-08. Kenting, Taiwan .
  27. Ching-Chung Hu; De-Sheng Chen; Yi-Wen Wang,"Fast multilevel floorplanning for large scale modules ," the 2004 International Symposium on Circuits and Systems, Volume: 5 , 23-26, 2004-05. 加拿大溫哥華 .
  28. Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Robust Fixed-outline Floorplanning Through Evolutionary Search ," IEEE/ACM 2004 Asia and South Pacific Design Automation Conference, pp 42~44, 2004-01. Yokohama, Japan .
  29. Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang,"Robust Fixed-outline Floorplanning Through Evolutionary Search ," 2003 VLSI Design/CAD Symposium, pp 9~12, 2003-08. 花蓮 .
  30. De-Sheng Chen, Chang-Tzu Lin, and Yi-Wen Wang,"Non-Slicing Floorplans with Boundary Constraints Using Generalized Polished Expression ," IEEE/ACM 2003 Asia and South Pacific Design Automation Conference 2003, pp 342-345, 2003-01. 日本、九州 .
  31. Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang,"An Efficient Gentic Algorithm for Slicing Floorplan Area Optimizition ," IEEE ISCAS 2002, 879~882, 2002-05. USA、Phoenix .
  32. Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang、I-Tsung Chen,"A Fast Evolutational Algorithm for Slicing Floorplans ," Proceedings of Proceedings of the 12th VLSI Design/CAD Symposium, CD-ROM, 2001-08. Hsin-Chu Taiwan .
  33. S. W. Chen, C. W. Hsu, Y. W. Wang, D. S. Chen, C. T. Lin, and S. F. Hwang,"VLSI implementations of a multicasting shared buffer for QoS multimedia networks ," Proceedings of the 11th VLSI Design/CAD Symposium, pp. 217-220, 2000-08. - .
  34. 曾憲輝、王益文、何應斌,"以複雜可程式邏輯元件實現適應共振理論(一)類神經網路晶片之學習電路 ," 1999自動控制研討會, pp.470~475, 1999-03. 中興大學，台中 .
  1. 專業書籍/王 壘, 袁世一, 王益文, 陳德生/ARM Cortex-M3 32位元微控制器原理與應用－HT32F1655/1656/ 全華科技圖書/中華民國/2017-04-01/310/ /
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  2. 神經網路加密演算法之研究/2016-07~2017-02/ 105-2815-C-035-100-E/主持人
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  4. 適用於低端設備的AES加解密/2012-07~2013-02/ NSC101-2815-C-035-048-E/主持人
  5. 可重組式類神經網路計算架構/2000-08~2001-07/ NSC89-2215-E-035-017/主持人
  6. VLSI實作共享緩衝器交換機架構/1998-08~1999-07/ NSC88-2215-E-035-005/主持人
  7. 類神經網路在網路上應用之研究/1997-08~1998-07/ NSC87-2213-E-035-024/主持人
  8. 動態網路交通塑型器之設計實作/2001-08~2002-07/ NSC90-2215-E-035-005/主持人
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  10. 嵌入式系統晶片之架構探究(1/3)/2004-08~2005-07/ NSC93-2215-E-035-006-/主持人
  11. 嵌入式系統晶片之架構探究(2/3)/2005-08~2006-07/ NSC94-2215-E-035-001-/主持人
  12. 嵌入式系統晶片之架構探究(3/3)/2006-08~2007-07/ NSC95-2221-E-035-122-/主持人
  13. 嵌入式系統之特定應用架構研究(I)/2009-08~2010-07/ NSC98-2221-E-035-061-/主持人
  14. 可重組式計算架構之單晶片系統(II)/2003-08~2004-07/ NSC92-2218-E-035-005-/主持人
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  17. 嵌入式系統之特定應用架構研究(III)/2011-08~2012-07/ NSC100-2221-E-035-102-/主持人
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  19. VLSI實作多點廣播共享緩衝器交換機架構/1999-08~2000-07/ NSC89-2215-E-035-005/主持人
  20. 保障網路服務品質之影像過濾器架構/1999-08~2000-07/ NSC89-2213-E-035-027/共同主持人
  21. 蒙哥馬利模數乘法之平行化架構研究/2013-08~2014-07/ NSC 102-2221-E-035-036-/共同主持人
  22. 神經網路加密演算法之客製化指令設計分析/2014-08~2015-07/ MOST103-2221-E-035-053-/主持人
  23. 混合巨集區塊與標準元件設計的平面規劃/2003-08~2004-07/ NSC92-2218-E-035-006-/共同主持人
  24. 特定應用導向多處理器系統單晶片設計方法(I)/2007-08~2008-07/ NSC96-2221-E-035-103-/主持人
  25. 神經網路軟體/硬體協同設計以語音增強為例/2016-08~2017-07/ MOST105-2221-E-035-083-/主持人
  26. 類神經網路之VLSI晶片研製及其即時系統之應用/1994-08~1995-07/ NSC 84-2215-E-035-007/主持人
  27. 類神經網路之VLSI晶片研製及其即時系統之應用(二)/1995-08~1996-07/ NSC 85-2215-E-035-003/主持人
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  30. 以即時通訊系統為基礎的離散式計算機架構/2004-01~2004-12/ NSC93-2623-7-035-001/協同/顧問
  31. 具有信號處理能力的嵌入式微處理機的實現及應用-子計畫二：嵌入式微處理機的晶片實現/2000-08~2001-07/ NSC89-2218-E-035-014/共同主持人
  1. 基板設計再利用/2021-09~2021-12/ 共同主持人
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  7. 印前審查流程自動化之人工智慧技術研發/2019-09~2020-10/ 共同主持人
  8. VLSI教育改進計畫- 數位系統之快速雛型製作(教材補助-26)/1998-03~1998-12/ 主持人
  9. 「超大型積體電路與系統設計」教育改進計畫─「PCI匯流排」課程/2002-01~2002-12/ 主持人
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  11. 超大型積體電路與系統設計教育改進計畫─聯盟發展計畫：「SOC System Overview」課程/2003-03~2003-12/ 主持人
  12. 通訊科技教育改進計畫 - 國內種子教師補助計畫 - 寬頻網際網路組 - 嵌入式系統設計與實務/2004-03~2004-12/ 主持人
  1. 101/協助辦理2012科技台灣探索(候烏計畫)」，圓滿達成任務，深獲學員、家長及海外人士之肯定 /行政院國家科學委員會/ 2012-10-23/行政院國家科學委員會民國101年10月23日臺會合字第1010070487號
  2. 92/大學校院積體電路設計競賽優等 /教育部/ 2004-07-09/92學年度FPGA組Altera設計類
  1. 107/逢甲大學優良教材獎勵優等獎/逢甲大學/ 2018-11-15/ARM Cortex-M3 32位元微控制器原理與應用－HT32F1655/1656
  2. 105/逢甲大學優良教材獎勵佳作獎/逢甲大學/ 2016-11-15/把智慧嵌入這個大千世界
  3. 97/逢甲大學論文著作獎勵傑出獎/逢甲大學/ 2008-11-15/Fixed-Outline Floorplanning Using Robust Evolutionary Search
  4. 96/逢甲大學論文著作獎勵優良獎/逢甲大學/ 2007-11-15/A Robust Genetic Algorithm for Rectangle Packing Problem
  5. 96/逢甲大學論文著作獎勵優良獎/逢甲大學/ 2007-11-15/VLSI Floorplanning with Boundary Constraints Using Generalized Polish Expression
  6. 96/逢甲大學論文著作獎勵優良獎/逢甲大學/ 2007-11-15/Modern Floorplanning with Boundary and Fixed-Outline Constraints via Genetic Clustering Algorithm
  1. 晶片系統設計(SOC)概論/致理技術學院商業自動化與管理系/2007-05
  2. Hardware/Software Co-Design for Embedded System Application/朝陽大學/2003-11
  3. 2003 SOC 系統晶片 RISC32:(後PC時代)/逢甲大學 2003 SOC 系統晶片高峰/2003-09
  1. None/雲端學院/把智慧嵌入這個大千世界/ 王 壘, 王益文, 陳德生, 袁世一/磨課師課程
Last update：2024-4-26, 9:26 a.m. Next update：2024-4-27, 9 a.m.